Semiconductor manufacturing is all about yield. A leading foundry used Cyc to model electrical parameters and test structures, physical chip characteristics, and the underlying manufacturing processes in order to augment their statistical yield analyses with a semantic (causal) assessment of end-to-end wafer manufacturing.
By incorporating the knowledge of various specialists into a single unified system, one yield engineer could perform more complete root-cause analysis enabling both:
- more experimental iterations during the design process, and
- quicker response time to yield deviations during production.
- This also saved a large factor of total engineer-hours, which is significant not due to saving salary dollars but rather due to the scarcity such engineers at that skill/experience level.